SC16C754IB80,528 NXP Semiconductors, SC16C754IB80,528 Datasheet - Page 25

• Manufacturer Part Number: SC16C754IB80,528
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754IB80,528

• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270057528; SC16C754IB80-T; SC16C754IB80-T

Philips Semiconductors
9397 750 11618
Product data
7.5 Line status register (LSR)
Table 13
Table 13:
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at
the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not
physically exist, as the data read from the RX FIFO is output directly onto the output
data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified
by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only
when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the RX FIFO read pointer. The
RX FIFO read pointer is incremented by reading the RHR.
Bit
7
6
5
4
3
2
1
0
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
LSR[1]
LSR[0]
shows the line status register bit settings.
Line Status Register bits description
Description
FIFO data error.
THR and TSR empty. This bit is the Transmit Empty indicator.
THR empty. This bit is the Transmit Holding Register Empty indicator.
Break interrupt.
Framing error.
Parity error.
Overrun error.
Data in receiver.
Rev. 04 — 19 June 2003
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error, or break indication is
in the receiver FIFO. This bit is cleared when no more errors are
present in the FIFO.
Logic 0 = Transmitter hold and shift registers are not empty.
Logic 1 = Transmitter hold and shift registers are empty.
Logic 0 = Transmit hold register is not empty.
Logic 1 = Transmit hold register is empty. The processor can now load
up to 64 bytes of data into the THR if the TX FIFO is enabled.
Logic 0 = No break condition (normal default condition).
Logic 1 = A break condition occurred and associated byte is 00, i.e.,
RX was LOW for one character time frame.
Logic 0 = No framing error in data being read from RX FIFO (normal
default condition).
Logic 1 = Framing error occurred in data being read from RX FIFO, i.e.,
received data did not have a valid stop bit.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error in data being read from RX FIFO.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error has occurred.
Logic 0 = No data in receive FIFO (normal default condition).
Logic 1 = At least one character in the RX FIFO.
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
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