ISD5008SY Nuvoton Technology Corporation of America, ISD5008SY Datasheet - Page 30

• Manufacturer Part Number: ISD5008SY
• Description: IC VOICE REC/PLAY 4-8MIN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5008r

Specifications of ISD5008SY

• Interface: SPI/Microwire
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 4 ~ 8 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To select this mode, the following control bits must be configured in the ISD5008 configuration
registers. To set up the transmit path:
1.
2
To set up the receive path:
1. Set up the ANA IN amplifier for the correct gain—Bits AIG0 and AIG1 control the gain settings
2. Power up the ANA IN amplifier—Bit AIPD controls the power up state of ANA IN. This is bit
3. Select the ANA IN path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of
4. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and
.
of this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin
determines the setting of this gain stage. Table 4 will help determine this setting. In this
example we will assume that the peak signal never goes above 1 volt p-p single ended. T
would enable us to use the 9dB attenuation setting, or where D14 is ONE and D15 is ZERO.
D13 of CFG0 and should be a ZERO to power up the amplifier.
the OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to
the state where D3 is ONE and D4 is ZERO to select the ANA IN path.
AUX amplifiers. These are bits D1 and D2 respectively of CFG0. They shou
state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and
Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control
the state of the ANAOUT MUX. These are the D6, D7 and D8 bits respectively of
Configura tion Register 0
Power up the ANA OUT amplifier—Bit AOPD controls the power up state of ANA OUT.
This is bit D5 of CFG0 and it should be a ZERO to power up the amplifier.
Chip Set
Chip Set
Chip Set
Microphone
Microphone
Microphone
ANA IN
ANA IN
ANA IN
MIC+
MIC+
MIC+
MIC–
MIC–
MIC–
2
2
2
( )
( )
( )
ANA IN
ANA IN
ANA IN
AMP
AMP
AMP
AIG0
AIG0
AIG0
AIG1
AIG1
AIG1
(CFG0) and they should all be ZERO to select the FTHRU path.
6dB
6dB
6dB
1
1
1
(AIPD)
(AIPD)
(AIPD)
OUTPUT
OUTPUT
FTHRU
FTHRU
FTHRU
SUM1
SUM1
SUM1
SUM2
SUM2
SUM2
FILT0
FILT0
FILT0
MUX
MUX
- 30 -
VOL
VOL
VOL
INP
INP
INP
ANA IN
ANA IN
ANA IN
FILTO
FILTO
FILTO
SUM 2
SUM 2
SUM 2
VOL
VOL
VOL
3
3
3
( )
( )
( )
( )
ANAOUT
ANAOUT
ANAOUT
MUX
MUX
MUX
AOS0
AOS0
AOS0
AOS0
AOS1
AOS1
AOS1
AOS1
AOS2
AOS2
AOS2
AOS2
2
2
2
( )
( )
( )
(AOPD)
(AOPD)
(AOPD)
OPS0
OPS0
OPS0
OPS1
OPS1
OPS1
1
1
1
Publication Release Date: Oct 31 2008
2
2
2
( )
( )
( )
OPA0
OPA0
OPA0
OPA1
OPA1
OPA1
Chip
Chip
Chip
Set
Set
Set
ANA OUT+
ANA OUT+
ANA OUT+
ANA OUT–
ANA OUT–
ANA OUT–
Speaker
Speaker
Speaker
SP+
SP+
SP+
SP–
SP–
SP–
ld be set to the
ISD5008
Revision 1.2
hat