ISD5008SY Nuvoton Technology Corporation of America, ISD5008SY Datasheet - Page 33

• Manufacturer Part Number: ISD5008SY
• Description: IC VOICE REC/PLAY 4-8MIN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5008r

Specifications of ISD5008SY

• Interface: SPI/Microwire
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 4 ~ 8 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.3
The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
Sto
and is not active in this mode. The path to be used is microphone input to AGC amplifier, then through
the INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the
FIL
STORAGE
be powered down.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CF
Only those portions necessary for this mode are powered up.
G1=0000 0001 0100 1000 (hex 0148).
TER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL
rage Array. A connected cellular telephone or cordless phone chip set may remain powered down
1.
2.
3.
4.
5.
6.
7.
Memo Record
ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may
Power up the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 of CFG1 and should be set to ZERO to
Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state
of the INPUT SOURCE MUX. This is bit D9 of CFG0 and should be set
select the AGC amplifier.
Select the INPUT SOURCE M
and S1M1 control the state of t
respectively of CFG1 and they should be set to t
ONE to select the INPUT SOURCE MUX (only) path.
Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls
the state of the FILTER
select the SUM1 SUMMING amplifier path.
Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW
PASS FILTER stage. This is bit D1 of CFG1 and it should be set to ZERO to power up the
LOW PASS FILTER stage.
Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting
and
CFG1. To enable the 5.3 kHz sample rate, D2 should be set to ZERO and D3 set to ONE.
Select the LOW PASS FILTER input (only) to the SUM2 SUMMING amplifier—Bits S2M0
and S2M1 control the state of the SUM2 SUMMING amplifier. These bits are D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is
ONE to select the LOW PASS FILTER (only) path.
sample rate to be used during record and playback. These are bits D2 and D3 of
MUX. This is bit D4 of CFG1 and it should be set to ZERO to
he SUM1 SUMMING amplifier. These are bits D7 and D8
UX (only) to the SUM1 SUMMING amplifier—Bits S1M0
- 33 -
he state where D7 is ZERO and D8 is
power up the stage.
Publication Release Date: Oct 31 2008
ISD5008
to a ZERO to
Revision 1.2