ISD5008SY Nuvoton Technology Corporation of America, ISD5008SY Datasheet - Page 34

• Manufacturer Part Number: ISD5008SY
• Description: IC VOICE REC/PLAY 4-8MIN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5008r

Specifications of ISD5008SY

• Interface: SPI/Microwire
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 4 ~ 8 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.4
This
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage.
From
the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a
pizeo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be
powered down.
1.
2.
3.
4.
5.
6.
7.
8.
9.
mode sets the chip up for local playb
there the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through
Memo and Call Playback
Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0
controls the state of the FILTER MUX. This is bit D4 of CFG1 and should be set to ONE to
select the MULTILEVEL STORAGE ARRAY.
Power up the LOW PASS FILTER—Bit FLPD controls the power up of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it should be set to ZERO to power up the LOW
PASS FILTER stage.
Select the 8.
and sample rate to be used during record and playback. These are bits D2 and D3 of
CFG1. To enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0
and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively
ONE to select the LOW PASS FILTER (only) path.
Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS
VLS1 control the state VOLUME MUX. These bits are D14 and D15, respecti
CFG1. They should be set to t
SUM2 SUMMING amplifier.
Power up the VOLUME CONTROL LEVEL—Bit V
VOLUME CONTROL attenuator. This is bit D0 of CFG0. This bit should be set a ZERO to
power up the VOLUME CONTROL.
Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1 and VOL2 control the state fo
the VOLUME CONTROL LEVEL. Theses are bits D11, D12 and D13, repectively of
CFG1. A binary count of 000 through 111 controls the amount of attenuation throught that
state. In most cases, the software will select an attenuation level according to the desires
of the current users of the product. In this example, we will assume the user wants an
attenuation of –12 dB. For that setting, D11 should be set to ONE, D12 should be set to
ONE, and D13 shoulde be set to ZERO.
Select the VOLUME CONTROL path through the OUTPUT MUX—Bits OPS0 and OPS1
control the state of the OUTPUT MUX. These are bits D3 and D4, respectively of CFG0.
They should be set to the state where D3 and D4 are ZERO to select the VOLUME
CONTROL.
Power up the SPEAKER amplifier and select the HIGH GAIN mode—Bits OPA0 and
OPA1 control the state of the speaker (SP+ and SP-) and AUX OUT outputs. These are
bits D1 and D2 of CFG0. They should be set to the state where D1 is ONE and D2 is
ZERO to power up the speaker outputs in the HIGH GAIN mode and to power down the
AUX OUT.
of CFG1 and they should be set to the state where D5 is ZERO and D6 is
0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting
ack of messages recorded earlier. The playback path is from
he state where D14 is ONE and D15 is ZERO to select the
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LPD controls the power up state of the
Publication Release Date: Oct 31 2008
ISD5008
Revision 1.2
vely of
0 and