ISD5008SY Nuvoton Technology Corporation of America, ISD5008SY Datasheet - Page 31

• Manufacturer Part Number: ISD5008SY
• Description: IC VOICE REC/PLAY 4-8MIN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5008r

Specifications of ISD5008SY

• Interface: SPI/Microwire
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 4 ~ 8 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The end result of the above set up is:
Sin
registers must be loaded in this order. The internal set up for both registers will take effect
synchronously with the rising edge of
ce both registers are being loaded, CFG0 is loaded followed by the loading of CFG1. These two
The status of the rest of the functions in the ISD5008 chip must be defined before the
con
1. Power down the Volume Control Element—Bit VLPD controls
2. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input
3. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM
4.
5. Power down the AGC amplifier—Bit AGPD controls the power
6. Don’t Care bits—The following stages are not used in Feed Through Mode. Their bits may be
figuration registers settings are updated:
configures it for it’s higher gain setting for use with a piezo speak
down the AUX output stage.
Volume Control. This is bit D0 fo CFG0 and it should be set to a ONE to power down
statge.
amplifier. This is bit D10 of CFG0 and it
mixer and bits
and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down the
stage.
Power down the FILTER stage—Bit FLPD
the device. This is bit D0 in CFG1 and s
This is bit D0 in CFG1 and should be set to
set to either level. In this example we will set all the following bits to ZERO.
CFG0 = 0100 0100 0000 1011 (hex 4408)
and
CFG1 = 0000 0001 1110 0011 (hex 01E3)
a. Bit INS0, bit D9 of CFG0 controls the Input Source Mux.
b. Bits AXG0 and AXG1
c. Bits FLD0 and FLD1 are bits D2 and D3 respectively in CFG1. They control the
d. Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX.
e. Bits S1S0 and S1S1 are bits D9 and D10 of CFG1. They control the SUM1 MUX.
f.
g. Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control
AUX IN amplifier gain setting.
sample
Bits VOL0, VOL1 and VOL2 are bits D11, D12 a
setting of the Volume Control.
Mux.
S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1
rate and filter band pass setting.
SS .
ar bits D11 and D12 respectively in CFG0. They control the
e
hould be set to a ONE to power down the stage.
should be set to a ONE to power down the stage.
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controls the power up state of the FILTER stage in
a ONE to power down the stage.
Publication Release Date: Oct 31 2008
nd D13 of CFG1. They control the
up state of the AGC amplifier.
er element and also powers
the power up state of the
ISD5008
Revision 1.2
the