ISD5008SY Nuvoton Technology Corporation of America, ISD5008SY Datasheet - Page 7

• Manufacturer Part Number: ISD5008SY
• Description: IC VOICE REC/PLAY 4-8MIN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5008r

Specifications of ISD5008SY

• Interface: SPI/Microwire
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 4 ~ 8 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5
MIC+ / MIC-
ANAOUT+ /
ANAOUT-
PIN NAME
V
SSD
PIN DESCRIPTION
SCLK
MOSI
MISO
SS
/ V
SSA
PDIP/SOIC
9, 15, 23
11 / 12
8 / 10
5, 6 /
2
1
3
4
12, 13 /
16 / 17
18 / 19
TSOP
2, 15,
10
11
22
8
9
Serial Clock: The SCLK is the clock input to the ISD5008.
Generated
synchronizes data transfers in and out of the device through
the MISO and MOSI lines.
Slave Select: This input, when LOW, selects the device.
Master Out Slave In: MOSI is the serial data input to the
ISD5008 device. The master microcontroller places data to be
clocked into the ISD5008 device on the MOSI line one-half
cycle before the rising edge of SCLK. Data is clocked into the
device with LSB (Least Significant Bit) first.
Master In Slave Out: MISO is the serial data output of the
ISD5008. Data is clocked out on the falling edge of SCLK. This
output goes into a high-impedance state when the device is not
selected. Data is clocked out of the device with LSB first.
Ground: The ISD5008 utilizes separate analog and digital
ground busses. The analog ground (V
together as close to the package as possible and connected
through a low-impedance path to power supply ground. The
digital ground (V
separate low-impedance path to power supply ground. These
ground paths should be large enough to ensure that the
impedance between the V
than 3 Ω. The backside of the die is connected to V
the substrate resistance. In a chip-on-board design, the die
attach area must be connected to V
Microphone +/–: The microphone inputs transfer the voice
signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The AGC circuit
has a range of 45dB in order to deliver a nominal 694 mVp-p
into the storage array from a typical electret microphone output
of 2 to 20 mVp-p. The direct path to the ANA OUT MUX has a
gain of 6dB so a 208 mVp-p signal across the differential
microphone inputs would give 416 mVp-p across the ANA OUT
pins. The input impedance is typically 10 kΩ.
Analog Outputs: These differential outputs are designed to
match to the microphone input of the telephone chip set. It is
designed to drive a minimum of 5 kΩ between the “+” and “–”
pins to a nominal voltage level of 700 mVp-p. Both pins have
DC bias of approximately 1.2 VDC. The AC signal is
superimposed upon this analog ground voltage. These pins
can be used single-ended, getting only half the voltage. Do
NOT ground the unused pin.
- 7 -
by
the
SSD
) pin should be connected through a
master
FUNCTION
Publication Release Date: Oct 31 2008
SSA
pins and the V
microcontroller,
SSD
.
SSA
) pins should be tied
SSD
ISD5008
Revision 1.2
pins is less
the
SSD
through
SCLK