ISD5008SY Nuvoton Technology Corporation of America, ISD5008SY Datasheet - Page 32

• Manufacturer Part Number: ISD5008SY
• Description: IC VOICE REC/PLAY 4-8MIN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5008r

Specifications of ISD5008SY

• Interface: SPI/Microwire
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 4 ~ 8 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.2
The call record mode adds the ability to record the incoming phone call. In most applications, the
ISD
record the incoming call, the set up of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz sample rate during recording.
The
SU
FILTER MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed
Through
pa
In
chip not required to add the record path remain powered down. In fact, CFG0 does not change and
remains
CFG0=0100 0100 0000 1011 (hex 440B).
CF
CFG1=0000 0000 1100 0101 (hex 00C5).
Sin
wo
th to the Multilevel Storage array from that point:
this mode, the elements of the original PASS THROUGH mode do not change. The sections of the
uld be necessary to load both registers.
G1 changes to
M2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, TH
ce CFG0 is not changed, it is only necessary to load CFG1. Note that if only CFG0 was changed, it
5008 would first be set up for Feed Through Mode as described above. When the user wishes to
1.
2.
3.
4.
5.
6.
block diagram of the ISD5008 shows that the Multilevel Storage array is always driven from the
Call Record
Mode has already powered up the ANA IN amp so we only need to power up and enable the
Select the ANA IN path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of
the SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set
to the state where both D9 and D10 are ZERO to select the ANA IN path.
Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 S
of CFG1
the SUM
Select the SUM1 SUMMING a
the state of the FILTER MUX. This is bit D4 of CFG1 and it should be set to ZERO to
select the SUM1 SUMMING amplifier path.
Power up the LOWPASS FI
LOWPASS FILTER stage. This is bit D1 of CFG1 and it should be set to ZERO to power
up the LOW PASS FILTER STAGE.
Select the 6.4
and sample rate to be used during record and playback. These are bits D2 and D3 of
CFG1. To enable the 6.4 kHz sample rate, D2 should be set to ONE and D3 to ZERO.
Select the LOW PASS FILTER input (only) to the SUM2 SUMMING amplifier—Bits S2M0
and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is
ONE to select the LOW PASS FILTER (only) path.
1 MUX (only) path.
and they should be set to the state where D7 is ONE and D8 is ZERO to select
kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting
mplifier path through the FILTER MUX—Bit FLS0 controls
LTER—Bit FLPD controls the power up state of the
UMMING amplifier. These are bits D7 and D8 respectively
- 32 -
Publication Release Date: Oct 31 2008
ISD5008
Revision 1.2
E