HDMP-1022 Agilent Technologies, Inc., HDMP-1022 Datasheet
HDMP-1022
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HDMP-1022 Summary of contents
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... Implement SCI-FI Standard • Implement Serial HIPPI Specification Description The HDMP-1022 transmitter and the HDMP-1024 receiver are used to build a high-speed data link for point-to-point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user’ ...
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... A) 16/20 BIT SIMPLEX TRANSMISSION MUX Tx CLK B) 32/40 BIT SIMPLEX TRANSMISSION Tx CLK Tx CLK C) 32/40 BIT SIMPLEX TRANSMISSION WITH HIGH CLOCK RATES Tx CLK Rx CLK D) 16/20 BIT DUPLEX TRANSMISSION Tx CLK E) SIMPLEX BROADCAST TRANSMISSION Figure 1. Various Configurations Using the HDMP-1022/1024. Rx CLK Rx DEMUX CLK Rx CLK Rx CLK Rx CLK Tx CLK Rx CLK Rx CLK Rx ...
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... This technique is recom- mended whenever operating near the maximum and minimum of two word rate ranges. The above information also applies to the HDMP-1022/1024 chipset when operating in 16 bit mode. PRE-RELEASE PRODUCT DISCLAIMER This product is in development at the Hewlett-Packard CSSD in San Jose, California ...
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... All values in this table are expected for a BER less than 5 25 0/0 0/1 380 1/0 190 1/1 110 320 100 500 Figure 2. Typical 16-bit Mode Data Rates. HDMP-1022 (Tx), HDMP-1024 (Rx) Typical Operating Rates for 20 Bit Mode + 4 5 Parallel Word Rate (Mword/sec) DIV1 DIV0 Range 0 0 29.2 62.5 (max 14.6 ...
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... C-FIELD DAV* ENCODER FLAG D0-D19 D-FIELD ENCODER RST* Figure 4. HDMP-1022 Transmitter Block Diagram. HDMP-1022 Tx Block Diagram The HDMP-1022 was designed to accept bit wide parallel data (frames) and transmit it over a high speed serial line, while minimizing the user’s necessary interface to the high speed cir- cuitry ...
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The type of fill frames sent (FF0 or FF1) is determined by the FF input duplex system normally connected to the Rx’s STAT1 pin. The ...
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... VCO Figure 5. HDMP-1024 Receiver Block Diagram. HDMP-1024 Rx Block Diagram The HDMP-1024 receiver was designed to convert a serial data signal sent from the HDMP-1022 into either 16,17, 20 bit wide parallel data. In doing this, it performs the functions of • Clock Recovery • Data Recovery • Demultiplexing • ...
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Clock Select The Clock Select accepts the high speed digital signal from the VCO and outputs an internal high speed serial clock. The VCO frequency is divided, based on the DIV1/DIV0 inputs, to the input signal’s frequency range. The Clock ...
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... MDFSEL = 1 D00 - D19 ED, FF DAV*, CAV* FLAG t s STRBOUT DOUT HCLK Figure 6. HDMP-1022 (Tx) Timing Diagram. 624 rate. The data must be valid before it’s sampled for a set-up time (t ), and remain valid after s it’s sampled for a hold time ( single frame mode ...
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... D00 - D19 LINKRDY* DAV*, CAV* FF, ERROR FLAG t d2 STAT1 STAT0 Figure 7. HDMP-1024 (Rx) Timing Diagram. The synchronous outputs, D0-D19, LINKRDY*, DAV*, CAV*, FF, ERROR, and FLAG, are updated for every data frame, with a delay of t after the falling d1 edge of STRBOUT. There is a latency delay of two frames from ...
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... BLL t , BLL Fall Time, Terminated with coupled f BLL VSWR H50 Input VSWR i,H50 VSWR BLL Output VSWR o,BLL Note: 1. BLL outputs are measured with external 150 HDMP-1022 (Tx), HDMP-1024 (Rx) Typical Lock-Up Time DIV1 DIV0 HDMP-1022, msec Note: 1 ...
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... Link 3 Delay measured from the rising edge of the Tx STRBIN when the data frame is read to the falling edge of the Rx STRBOUT when the data frame is updated HDMP-1022 (Tx), HDMP-1024 (Rx) Absolute Maximum Ratings except as specified. Operation in excess of any one of these conditions may result in permanent A damage to this device ...
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... HDMP-1022 (Tx) Thermal Characteristics Symbol Thermal Resistance, Junction to Air. Measured in still air with the package ja mounted on a thermal test PCB per JEDEC standard JC -15.1 Thermal Resistance, Junction to Case. Top center of the package is used as jc the reference point P Power Dissipation HDMP-1024 (Rx) ...
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... HCLKON 10 HCLK 11 HDMP-1022 HCLK* 12 LLLL TX R. LOUT 14 LOUT DDDD C LOOPEN 16 DOUT 17 DOUT* 18 DIV0 19 DIV1 20 GND 21 GND Figure 8. HDMP-1022 (Tx) Package Layout, Top View. CAP0B 1 CAP0A 2 CAP1A 3 CAP1B DIV0 6 DIV1 TCLKSEL TCLK 12 HDMP-1024 ...
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Tx I/O Definition Name Pin Type CAP0A 2 C Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A CAP0B 1 should be shorted to CAP1B. A loop filter capacitor of 0.1 f must be CAP1A 3 connected across the ...
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Tx I/O Definition (cont’d.) Name Pin Type EHCLKSEL 78 I-TTL EHCLK Enable: When active, this input causes the STRBIN inputs to be used for the transmit serial clock, rather than the internal VCO clock. This is useful for generating extremely ...
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Tx I/O Definition (cont’d.) Name Pin Type LOUT 14 O-BLL Loop Back Serial Data Output: Output used when LOOPEN is LOUT* 15 active. Typically this output will be used to drive the LIN, LIN* inputs of the Rx chip. M20SEL ...
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Tx I/O Definition (cont’d.) Name Pin Type TTL Power Supply: Normally 5.0 volts. Used for all TTL transmitter CCTTL1 33 input buffer cells TTL Power Supply: Normally 5.0 volts. Used for all TTL transmitter ...
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Rx I/O Definition Name Pin Type ACTIVE 25 I-TTL Chip Enable: This input is normally driven by the Rx state machine output. The ACTIVE signal is internally retimed by STRBOUT and presented to the user as the LINKRDY signal. This ...
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Rx I/O Definition (cont’d.) Name Pin Type ERROR 40 O-TTL Received Data Error: Asserted when a frame is received that does not correspond to either a valid Data, Control, or Fill frame encoding. When FLAGSEL is not active, the Rx ...
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Rx I/O Definition (cont’d.) Name Pin Type SMRST0* 28 I-TTL State Machine Reset Inputs: Each of these active-low input pins SMRST1* 29 reset the Rx state machine to the initial start-up state. This initiates a complete PLL restart and handshake ...
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... ALL DIMENSIONS ARE IN MILLIMETERS (INCHES). Figure 10. Mechanical Dimensions of HDMP-1022 and HDMP-1024. dimensions conform to JEDEC plastic QFP specifications and are shown below in Figure 10. The M-Quad 80 package material is aluminum and the leads have been formed into a “Gull-Wing” ...
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... DATA FIELD 16/20 BITS SERIAL DATA FILL FRAME FRAME K Figure 11. HDMP-1022/1024 (Tx/Rx Pair) Line Code. 638 Detailed coding schemes are described in the following subsections. All the tables given in this section show data bits in the same configuration as a scope display. In other words, the ...
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... HDMP-1022 (Tx), HDMP-1024 (Rx) Data Frame Structure M20SEL Not Asserted (16 bit data mode) Data Status Flag bit True 0 Inverted 0 True 1 Inverted 1 HDMP-1022 (Tx), HDMP-1024 (Rx) Data Frame Structure M20SEL Asserted (20 bit data mode) Data Status Flag bit True 0 Inverted 0 True 1 Inverted 1 Control Frame Codes 18 ...
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... HDMP-1022 (Tx), HDMP-1024 (Rx) Fill Frame Structure M20SEL Not Asserted (16 bit mode) Fill Frame D-Field 0 1111111 1a 1111111 1b 1111111 HDMP-1022 (Tx), HDMP-1024 (Rx) Fill Frame Structure M20SEL Asserted (20 bit mode) Fill Frame D-Field 0 111111111 1a 111111111 1b 111111111 640 C-Field ...
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... Tx Operation Principles The HDMP-1022 (Tx) is imple- mented in a high performance silicon bipolar process. The Tx performs the following functions for link operation: • Phase lock to frame rate clock • Clock multiplication • Frame encoding • Multiplexing In normal operation, the Tx phase ...
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... M20SEL CLOCK GENERATOR MDFSEL LOCK DETECT STRBOUT LOCKED Figure 12. HDMP-1022 (Tx) Phase-Locked Loop. 642 between high and low for data frames. This allows the link to perform more extensive error detection when the extra bit is unused. ACCMSB is the sign of the pre- viously transmitted data. This is used to determine which type of FF1 should be sent ...
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... The data path consists of an Input Select, LOOPEN EQEN DIN CABLE EQ LIN Figure 13. HDMP-1024 (Rx) Input Selector. an Input Sampler, a Frame Demultiplexer, a Control Field (C- Field) Decoder, and a Data Field (D-Field) Decoder. An on-chip phase-locked loop (PLL) is used to extract timing reference from the serial input (DIN or LIN) ...
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... The frequency detector disable signal, FDIS, selects which detector to use. If synchronization in a link is not yet established, the HDMP-1022 (Tx) should send out Fill Frame 0 (FF0) or Fill Frame 1 (FF1) to the remote Rx. By setting FDIS=0, the Rx uses the frequency detector to align its internal clock with the rising edge of FF0/FF1 ...
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... Rx chip provides a link handshake protocol enabling the duplex link to transition from frequency acquisition and training mode into data mode. The HDMP-1022/1024 Tx/Rx link uses an explicit frequency acquisition mode at startup that operates on a square-wave training sequence. This makes it possible to use a VCO with a very ...
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... ENABLE DATA RECEPTION FREQUENCY DETECTOR OFF STATE STAT1 PIN Figure 15. HDMP-1024 (Rx) State Machine State Diagram. 646 slipping that occurs in the initial frequency acquisition of both the Tx and Rx PLLs. When the local port is in State the reset state, where both local Tx and Rx parallel interfaces are disabled ...
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... Since the data stream has no DC component, a coupling cap of 0 recommended for the DIN and LIN inputs. Full Duplex Figure 16 shows HDMP-1022/ 1024 in a full duplex configura- tion connecting two bidirectional (parallel) buses. Each end of the link has a Tx and Rx pair. The receiver’ ...
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Tx is ready to send data (RFD). Other configurations for duplex mode are also possible with external user-defined state machines. Simplex operation using G-LINK is also possible. The following sections ...
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Simplex Method II. Simplex with Periodic Sync Pulse. Another configuration of simplex operation is shown in Figure 17b. For frame lock, the Rx normally relies on either FF0 or FF1. In this example, the fill frame FF of the Tx ...
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... CAV*), must appear before the setup time t , and remain valid for the hold s time t . Refer to HDMP-1022 Tx h Timing. Since the PLL of the Tx is designed with a very high-gain frequency/phase detector, the relative alignment of the internal clock and STRBIN is very tight, and is insensitive to temperature and other variations ...
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Double Frame Mode (MDFSEL=1) A block diagram showing the double-frame mode data interface for both the Tx and Rx, and their associated timing diagrams are shown in Figure 17. This configuration works best if the duty cycle of STRBIN is ...
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... CAP0A C2 D1 CAP1A CAP1B HP HDMP-1022 LOT# DATECODE C1 R1 Figure 20a. HDMP-1022 (Tx) Power Supply Bypass HDMP-1024 LOT# Rx DATECODE BYPASS CAPACITOR C2 = PLL INTEGRATOR CAPACITOR D1 = OPTIONAL CLAMPING DIODE Figure 20b. HDMP-1022 (Rx) Power Supply Bypass 0.1 µF 0.1 µF ...
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The typical swing 0.8 volts, and thus, the clamping diode should have a turn-on voltage below 0.8 V, such as with germanium or schottky diodes. This will vary with each application. This diode will also ...
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O-BLL 0.1 µ Figure 22. I-H50 and O-BLL Simplified Circuit Schematic. Mode Options The GLlink has several option pins which set the modes of operation. Common to both the Tx and the Rx are ...
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OBLL SINGLE-ENDED DRIVE O-BLL TO I-H50 OBLL DIFFERENTIAL DRIVE O-BLL TO I-H50 Figure 23. Methods of Interfacing O-BLL and I-H50. OBLL IH50 C) DIFFERENTIAL ...