AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 337

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
Note:
Note:
3. Write the starting source address in the SARx register for channel x.
4. Write the channel configuration information into the CFGx register for channel x.
5. Make sure that the LLI.CTLx register locations of all LLIs in memory (except the last)
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last)
7. Make sure that the LLI.DARx register location of all LLIs in memory point to the start
8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing
10. Program the CTLx, CFGx registers according to Row 7 as shown in
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
14. Source and destination request single and burst DMACA transactions to transfer the
15.
16. The DMA transfer proceeds as follows:
– vi. Incrementing/decrementing or fixed address for destination DINC field.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
are set as shown in Row 7 of
last Linked List item must be set as described in Row 1 or Row 5 of
326.
are non-zero and point to the next Linked List Item.
destination block address proceeding that LLI fetch.
memory is cleared.
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
page
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
block of data (assuming non-memory peripherals). DMACA acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block
transfer.
Table 19-1 on page
Hardware sets the block complete interrupt. The DMACA samples the row number as
shown in
fer has completed. Hardware sets the transfer complete interrupt and disables the
channel. You can either respond to the Block Complete or Transfer Complete inter-
rupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by
hardware, to detect when the transfer is complete. If the DMACA is not in Row 1 or 5 as
shown in
The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in
memory, although fetched during a LLI fetch, are not used.
The LLI.SARx, LLI.DARx, LLI. LLPx and LLI.CTLx registers are fetched. The LLI.SARx register
although fetched is not used.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
Figure 19-7 on page 325
326.
Table 19-1 on page
Table 19-1 on page 326
326The DMACA reloads the SARx register from the initial value.
Table 19-1 on page 326
326. If the DMACA is in Row 1 or 5, then the DMA trans-
shows a Linked List example with two list items.
the following steps are performed.
while the LLI.CTLx register of the
Table 19-1 on page
Table 19-1 on
337