AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 785

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.5.2
28.5.3
28.5.4
28.5.5
28.5.6
28.6
28.6.1
28.6.2
28.6.3
32072G–11/2011
Functional Description
Power Management
Clocks
Interrupts
Analog Inputs
Timer Triggers
Analog-to-digital Conversion
Conversion Reference
Conversion Resolution
In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is
small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the
ADC behavior.
The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
ADC before disabling the clock, to avoid freezing the ADC in an undefined state.
The CLK_ADC clock frequency must be in line with the ADC characteritics. Refer to Electrical
Characteristics section for details.
The ADC interrupt request line is connected to the interrupt controller. Using the ADC interrupt
requires the interrupt controller to be programmed first.
The analog input pins can be multiplexed with I/O lines. In this case, the assignment of the ADC
input is automatically done as soon as the corresponding I/O is configured through the I/O con-
toller. By default, after reset, the I/O line is configured as a logic input.
Timer Counters may or may not be used as hardware triggers depending on user requirements.
Thus, some or all of the timer counters may be non-connected.
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-
bit digital data requires sample and hold clock cycles as defined in the Sample and Hold Time
field of the Mode Register (MR.SHTIM) and 10 ADC Clock cycles. The ADC Clock frequency is
selected in the Prescaler Rate Selection field of the MR register (MR.PRESCAL).
The ADC Clock range is between CLK_ADC/2, if the PRESCAL field is 0, and CLK_ADC/128, if
the PRESCAL field is 63 (0x3F). The PRESCAL field must be written in order to provide an ADC
Clock frequency according to the parameters given in the Electrical Characteristics chapter.
The conversion is performed on a full range between 0V and the reference voltage connected to
VDDANA. Analog input values between these voltages are converted to digital values based on
a linear conversion.
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by writing a one to
the Resolution bit in the MR register (MR.LOWRES). By default, after a reset, the resolution is
the highest and the Converted Data field in the Channel Data Registers (CDRn.DATA) is fully
used. By writing a one to the LOWRES bit, the ADC switches in the lowest resolution and the
conversion results can be read in the eight lowest significant bits of the Channel Data Registers
(CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read
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