AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 633

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.7.2.4
26.7.2.5
32072G–11/2011
Endpoint reset
Endpoint activation
An endpoint can be reset at any time by writing a one to the Endpoint n Reset (EPRSTn) bit in
the UERST register. This is recommended before using an endpoint upon hardware reset or
when a USB bus reset has been received. This resets:
Note that the interrupt sources located in the UESTAn register are not cleared when a USB bus
reset has been received.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to
the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data
Toggle Set bit in the Endpoint n Control Set register (UECONnSET.RSTDTS).(This will set the
Reset Data Toggle (RSTD) bit in UECONn).
In the end, the user has to write a zero to the EPRSTn bit to complete the reset operation and to
start using the FIFO.
The endpoint is maintained inactive and reset (see
it is disabled (EPENn is written to zero). DTSEQ is also reset.
The algorithm represented on
endpoint.
• The default control endpoint is reset (see
• The data toggle sequence of the default control endpoint is cleared.
• At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set.
• During a reset, the USBB automatically switches to the Hi-Speed mode if the host is Hi-
• The internal state machine of this endpoint.
• The receive and transmit bank FIFO counters.
• All the registers of this endpoint (UECFGn, UESTAn, the Endpoint n Control (UECONn)
Speed capable (the reset is called a Hi-Speed reset). The user should observe the
USBSTA.SPEED field to know the speed running at the end of the reset (EORST is one).
register), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and the Data
Toggle Sequence (DTSEQ) field of the UESTAn register.
Figure 26-13 on page 634
Section 26.7.2.4
Section 26.7.2.4
must be followed in order to activate an
for more details).
for more details) as long as
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