AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 375

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.12.22 DMA Configuration Register
Name:
Access Type:
Offset:
Reset Value:
• DMA_EN: DMA Controller Enable
This register is used to enable the DMACA, which must be done before any channel activity can begin.
If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns ‘1’ to indi-
cate that there are channels still active until hardware has terminated all activity on all channels, at which point the
DmaCfgReg.DMA_EN bit returns ‘0’.
32072G–11/2011
31
23
15
7
-
-
-
-
0 = DMACA Disabled
1 = DMACA Enabled.
30
22
14
6
-
-
-
-
DmaCfgReg
Read/Write
0x398
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
25
17
9
1
-
-
-
-
DMA_EN
24
16
8
0
-
-
-
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