AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 607

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.7.15
Name:
Access Type:
Offset:
Reset Value:
This register can only be written to if write protection is disabled, see
• DRIFT: Drift compensation
• RX_MPOL: Receiver Manchester Polarity
• RX_PP: Receiver Preamble Pattern detected
Table 25-24.
• RX_PL: Receiver Preamble Length
• TX_MPOL: Transmitter Manchester Polarity
32072G–11/2011
31
23
15
–
–
–
7
–
0
0
1
1
0: The USART can not recover from a clock drift.
1: The USART can recover from clock drift (only available in 16x oversampling mode).
0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transitions.
1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.
0: The receiver preamble pattern detection is disabled.
1 - 15: The detected preamble length is RX_PL x bit period
0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transitions.
1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.
Manchester Configuration Register
RX_PP
DRIFT
30
22
14
MAN
Read-write
0x50
0x30011004
–
–
6
–
0
1
0
1
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
Preamble Pattern default polarity assumed (RX_MPOL field not set)
29
21
13
1
–
–
5
–
RX_MPOL
TX_MPOL
28
20
12
–
4
–
27
19
11
–
–
3
”Write Protect Mode Register” on page
26
18
10
–
–
2
RX_PL
TX_PL
25
17
9
1
RX_PP
TX_PP
612.
24
16
8
0
607