AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 479

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.8.2.2
23.8.3
32072G–11/2011
Master Transmitter Mode
Setting up and Performing a Transfer
Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Reg-
ister (CMDR). TWIM status is provided in the Status Register (SR). The following list presents
the main steps in a typical communication:
The interrupt system can be set up to give interrupt requests on specific events or error condi-
tions in the SR, for example when the transfer is complete or if arbitration is lost. The Interrupt
Enable Register (IER) and Interrupt Disable Register (IDR) can be written to specify which bits in
the SR will generate interrupt requests.
The SR.BUSFREE bit is set when activity is completed on the two-wire bus. The SR.CRDY bit is
set when CMDR and/or NCMDR is ready to receive one or more commands.
The controller will refuse to start a new transfer while ANAK, DNAK, or ARBLST in the Status
Register (SR) is one. This is necessary to avoid a race when the software issues a continuation
of the current transfer at the same time as one of these errors happen. Also, if ANAK or DNAK
occurs, a STOP condition is sent automatically. The user will have to restart the transmission by
clearing the error bits in SR after resolving the cause for the NACK.
After a data or address NACK from the slave, a STOP will be transmitted automatically. Note
that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the
VALID bit can be cleared manually allowing any command in NCMDR to be copied into CMDR.
When a data or address NACK is returned by the slave while the master is transmitting, it is pos-
sible that new data has already been written to the THR register. This data will be transferred out
as the first data byte of the next transfer. If this behavior is to be avoided, the safest approach is
to perform a software reset of the TWIM.
A START condition is transmitted and master transmitter mode is initiated when the bus is free
and CMDR has been written with START=1 and READ=0. START and SADR+W will then be
transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The
master polls the data line during this clock pulse and sets the Address Not Acknowledged bit
(ANAK) in the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data
bytes, ie START, SADR+W, STOP.
1. Before any transfers can be performed, bus timings must be configured by writing to
2. If the Peripheral DMA Controller is to be used for the transfers, it must be set up.
3. CMDR or NCMDR must be written with a value describing the transfer to be performed.
1. Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY
2. Transmit this data byte
3. Decrement NBYTES
4. If (NBYTES==0) and STOP=1, transmit STOP condition
the Clock Waveform Generator Register (CWGR). If operating in SMBus mode, the
SMBus Timing Register (SMBTR) register must also be configured.
indicates the state of THR. Software or the Peripheral DMA Controller must write the
data byte to THR.
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