AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 413

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 21-8. Peripheral Deselection
21.7.3.9
32072G–11/2011
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
Write TDR
Write TDR
Write TDR
Write TDR
TDRE
TDRE
TDRE
TDRE
Mode fault detection
PCS = A
A
A
A
A
CSAAT = 0 and CSNAAT = 0
CSAAT = 0 and CSNAAT = 0
DLYBCT
DLYBCT
DLYBCT
DLYBCT
Figure 21-8 on page 413
CSRn.CSAAT and CSRn.CSNAAT bits.
The SPI is capable of detecting a mode fault when it is configured in master mode and NPCS0,
MOSI, MISO, and SPCK are configured as open drain through the I/O Controller with either
internal or external pullup resistors. If the I/O Controller does not have open-drain capability,
mode fault detection must be disabled by writing a one to the Mode Fault Detection bit in the MR
DLYBCS
DLYBCS
DLYBCS
PCS = B
PCS=A
A
PCS = A
A
B
shows different peripheral deselection cases and the effect of the
A
PCS = A
A
A
A
A
CSAAT = 0 and CSNAAT = 1
CSAAT = 1 and CSNAAT= 0 / 1
DLYBCT
DLYBCT
DLYBCT
DLYBCT
DLYBCS
DLYBCS
PCS = B
PCS = A
DLYBCS
A
A
PCS = A
DLYBCS
A
A
A
B
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