AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 952

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.5.4.2
34.5.4.3
32072G–11/2011
Reset register
Boundary-Scan Chain
The reset register is selected by the AVR_RESET instruction and contains one bit for each reset
domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared.
Note: This register is primarily intended for compatibility with other 32-bit AVR devices. Certain
operations may not function correctly when parts of the system are reset. It is generally recom-
mended to only write 0x11111 or 0x00000 to these bits to ensure no unintended side effects
occur.
The Boundary-Scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the
internal logic. Typically, output value, output enable, and input data are all available in the
boundary scan chain.
The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file
available at the Atmel web site.
Bit
Device ID
CPU
APP
OCD
RSERVED
OCD
4
CPU
HSB and PB buses
On-Chip Debug logic and registers
No effect
APP
3
RESERVED
2
RESERVED
1
CPU
LSB
0
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