AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 315
AT32UC3B0256
Manufacturer Part Number
AT32UC3B0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
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Manufacturer:
ATMEL
Quantity:
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Part Number:
AT32UC3B0256-U
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Quantity:
20 000
Company:
Part Number:
AT32UC3B0256-Z2UT
Manufacturer:
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Quantity:
444
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 315 of 684
- Download datasheet (11Mb)
21.6.4.12
21.6.4.13
Figure 21-25. Break Transmission
21.6.4.14
32059L–AVR32–01/2012
Baud Rate
TXEMPTY
TXRDY
Clock
Write
TXD
CR
Framing Error
Transmit Break
Receive Break
Start
Bit
D0
D1
D2
STTBRK = 1
The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit
reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing
error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit.
Figure 21-24. Framing Error Status
When CSR.TXRDY is set, the user can request the transmitter to generate a break condition on
the TXD line by writing a one to The Start Break bit (CR.STTBRK). The break is treated as a nor-
mal 0x00 character transmission, clearing CSR.TXRDY and CSR.TXEMPTY, but with zeroes for
preambles, start, parity, stop, and time guard bits. Writing a one to the Stop Break bit
(CR.STBRK) will stop the generation of new break characters, and send ones for TG duration or
at least 12 bit periods, ensuring that the receiver detects end of break, before resuming normal
operation.
Writing to CR.STTBRK and CR.STPBRK simultaneously can lead to unpredictable results.
Writes to THR before a pending break has started will be ignored.
A break condition is assumed when incoming data, parity, and stop bits are zero. This corre-
sponds to a framing error, but FRAME will remain zero while the Break Received/End Of Break
D3
D4
D5
D6
Figure 21-25
Baud Rate
D7
FRAME
RXRDY
Parity
Bit
Clock
Write
RXD
CR
Stop
Bit
illustrates STTBRK and STPBRK effect on the TXD line.
Start
Bit
D0
Break Transmission
STPBRK = 1
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
End of Break
RSTSTA = 1
315
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