AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 403

• Manufacturer Part Number: AT32UC3B0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• ROLEEXI: Role Exchange Interrupt
• BCERRI: B-Connection Error Interrupt
• VBERRI: VBus Error Interrupt
• VBUSTI: VBus Transition Interrupt
• IDTI: ID Transition Interrupt
32059L–AVR32–01/2012
This bit is set when the USBB has successfully switched its mode because of an negotiation (host to device or device to host).
This triggers a USB interrupt if ROLEEXE is one.
This bit is cleared when the UBSTACLR.ROLEEXIC bit is written to one.
This bit is set when an error occurs during the B-connection. This triggers a USB interrupt if BCERRE is one.
This bit is cleared when the UBSTACLR.BCERRIC bit is written to one.
This bit shall only be used in host mode.
This bit is set when a VBus drop has been detected. This triggers a USB interrupt if VBERRE is one.
This bit is cleared when the UBSTACLR.VBERRIC bit is written to one.
This bit shall only be used in host mode.
If a VBus problem occurs, then the VBERRI interrupt is generated even if the USBB does not go to an error state because of
VBUSHWC is one.
This bit is set when a transition (high to low, low to high) has been detected on the USB_VBUS pad. This triggers an USB
interrupt if VBUSTE is one.
This bit is cleared when the UBSTACLR.VBUSTIC bit is written to one.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
This bit is set when a transition (high to low, low to high) has been detected on the USB_ID input pin. This triggers an USB
interrupt if IDTE is one.
This bit is cleared when the UBSTACLR.IDTIC bit is written to one.
This interrupt is generated even if the clock is frozen by the FRZCLK bit or pad is disable by USBCON.OTGPADE or the USBB
module is disabled by USBCON.USBE.
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