AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 285

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• DATNB: Data Number per Frame
• MSBF: Most Significant Bit First
• DATDEF: Data Default Value
• DATLEN: Data Length
32059L–AVR32–01/2012
DATLEN
Others
8-15
The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256
transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated during one transmit clock
period.
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).
1: The most significant bit of the data register is shifted out first in the bit stream.
0: The lowest significant bit of the data register is shifted out first in the bit stream.
This bit defines the level driven on the TX_DATA pin while out of transmission.
Note that if the pin is defined as multi-drive by the I/O Controller, the pin is enabled only if the TX_DATA output is one.
1: The level driven on the TX_DATA pin while out of transmission is one.
0: The level driven on the TX_DATA pin while out of transmission is zero.
The bit stream contains (DATLEN + 1) data bits.
This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the transmitter.
1-7
0
Transfer Size
Forbidden value (1-bit data length is not supported)
Data transfer are in bytes
Data transfer are in halfwords
Data transfer are in words
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