AT89C51ID2 Atmel Corporation, AT89C51ID2 Datasheet - Page 100

• Manufacturer Part Number: AT89C51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89C51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 2
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Functional Description
Operating Modes
4289C–8051–11/05
Figure 37 shows a detailed structure of the SPI Module.
Figure 37. SPI Module Block Diagram
The Serial Peripheral Interface can be configured in one of the two modes: Master
mode or Slave mode. The configuration and initialization of the SPI Module is made
through one register:
•
Once the SPI is configured, the data exchange is made using:
•
•
•
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 38).
SPI Interrupt Request
The Serial Peripheral Control register (SPCON)
SPCON
The Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral DATa register (SPDAT)
Clock
Divider
FCLK PERIPH
SPR2
/128
/16
/32
/64
SPEN
/8
/4
Clock
Select
SSDIS
MSTR
SPIF
Receive Data Register
CPOL
7
Shift Register
WCOL
Internal Bus
6
CPHA
SPI
Control
5
4
3
SPR1
-
2
Clock
Logic
SPCON
1
SPDAT
MODF
0
SPR0
-
AT89C51ID2
M
Pin
Control
Logic
S
-
-
SPSTA
-
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS
100