AT89C51ID2 Atmel Corporation, AT89C51ID2 Datasheet - Page 63

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AT89C51ID2

Manufacturer Part Number
AT89C51ID2
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C51ID2

Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
2
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes

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Interrupt System
Figure 25. Interrupt Control System
4289C–8051–11/05
EXF2
KBD IT
TWI IT
SPI IT
INT0
INT1
PCA IT
TF0
TF1
TF2
RI
TI
Individual Enable
The AT89C51ID2 has a total of 10 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt,
Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure
25.
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register (Table 52 and Table 50). This register also
contains a global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority register (Table 53) and in the
Interrupt Priority High register (Table 51 and Table 52) shows the bit values and priority
levels associated with each combination.
IE0
IE1
IPH, IPL
Global Disable
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
AT89C51ID2
Low priority
interrupt
63

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