AT89C51ID2 Atmel Corporation, AT89C51ID2 Datasheet - Page 102

• Manufacturer Part Number: AT89C51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89C51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 2
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Figure 39. Data Transmission Format (CPHA = 0)
Figure 40. Data Transmission Format (CPHA = 1)
Figure 41. CPHA/SS Timing
4289C–8051–11/05
MOSI (from Master)
SCK Cycle Number
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 0)
SCK (CPOL = 1)
MISO (from Slave)
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 1)
SCK (CPOL = 0)
Capture Point
SPEN (Internal)
SS (to Slave)
Capture Point
SS (to Slave)
MISO/MOSI
(CPHA = 0)
(CPHA = 1)
Master SS
Slave SS
Slave SS
As shown in Figure 39, the first SCK edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 41).
Figure 40 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmis-
sions (Figure 41). This format may be preffered in systems having only one Master and
only one Slave driving the MISO data line.
MSB
MSB
MSB
1
MSB
1
2
bit6
bit6
2
bit6
bit6
Byte 1
3
bit5
bit5
3
bit5
bit5
bit4
bit4
4
bit4
4
bit4
Byte 2
bit3
5
bit3
bit3
bit3
5
6
bit2
bit2
6
bit2
bit2
Byte 3
7
bit1
bit1
7
bit1
bit1
LSB
8
8
LSB
LSB
LSB
AT89C51ID2
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