AT89C51ID2 Atmel Corporation, AT89C51ID2 Datasheet - Page 111
AT89C51ID2
Manufacturer Part Number
AT89C51ID2
Description
Manufacturer
Atmel Corporation
Specifications of AT89C51ID2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
2
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes
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EEPROM Data
Memory
Write Data
4289C–8051–11/05
The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh
of the XRAM/ERAM memory space and is selected by setting control bits in the EECON
register.
A read or write access to the EEPROM memory is done with a MOVX instruction.
Data is written by byte to the EEPROM memory block as for an external RAM memory.
The following procedure is used to write to the EEPROM memory:
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Figure 43 represents the optimal write sequence to the on-chip EEPROM data memory.
Check EEBUSY flag
If the user application interrupts routines use XRAM memory space: Save and
disable interrupts.
Load DPTR with the address to write
Store A register with the data to be written
Set bit EEE of EECON register
Execute a MOVX @DPTR, A
Clear bit EEE of EECON register
Restore interrupts.
EEBUSY flag in EECON is then set by hardware to indicate that programming is in
progress and that the EEPROM segment is not available for reading or writing.
The end of programming is indicated by a hardware clear of the EEBUSY flag.
AT89C51ID2
111