ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 116
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ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Quantity
Price
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15.2.6
15.2.7
15.2.8
2549N–AVR–05/11
PCIFR – Pin Change Interrupt Flag Register
PCMSK2 – Pin Change Mask Register 2
PCMSK1 – Pin Change Mask Register 1
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt
Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.
• Bit 2 – PCIF2: Pin Change Interrupt Flag 1
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
0x1B (0x3B)
Read/Write
Initial Value
Bit
(0x6D)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
PCINT15
PCINT23
R/W
R/W
7
0
7
0
R
7
–
0
PCINT22
PCINT14
R/W
R/W
6
0
6
0
R
6
–
0
PCINT21
PCINT13
ATmega640/1280/1281/2560/2561
R/W
R/W
0
5
0
5
R
5
–
0
PCINT20
PCINT12
R/W
R/W
4
0
4
0
R
4
–
0
PCINT19
PCINT11
R/W
R/W
3
0
3
0
R
3
–
0
PCINT18
PCINT10
PCIF2
R/W
R/W
R/W
2
0
2
0
2
0
PCINT17
PCINT9
PCIF1
R/W
R/W
R/W
1
0
1
0
1
0
PCINT16
PCINT8
PCIF0
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK2
PCMSK1
PCIFR
116
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