ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 350
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ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega640-16AU
Manufacturer:
OSRAM
Quantity:
12 000
Part Number:
ATmega640-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega640V-8AU
Manufacturer:
PHILIPS
Quantity:
56
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30.8.1
30.8.2
2549N–AVR–05/11
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 30-15. Pin Mapping Serial Programming
Figure 30-10. Serial Programming and Verify
Notes:
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega640/1280/1281/2560/2561, data is clocked on the rising
edge of SCK.
When reading data from the ATmega640/1280/1281/2560/2561, data is clocked on the falling
edge of SCK. See
Symbol
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
PDO
SCK
PDI
XTAL1 pin.
programming the EEPROM, an auto-erase cycle is built into the self-timed programming oper-
ation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
CC
- 0.3V < AVCC < V
Figure 30-12 on page 353
(TQFP-100)
Pins
PB2
PB3
PB1
PDO
SCK
PDI
ck
ck
CC
ATmega640/1280/1281/2560/2561
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V.When
XT AL1
RESET
GND
(TQFP-64)
for timing details.
(1)
Pins
PE0
PE1
PB1
AVCC
VCC
+1.8V - 5.5V
+1.8V - 5.5V
I/O
O
I
I
(2)
ck
ck
>= 12MHz
>= 12MHz
Serial Data out
Serial Data in
Description
Serial Clock
350
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