ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 30
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ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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Manufacturer:
OSRAM
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12 000
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
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Part Number:
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Quantity:
56
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9.1.3
9.1.4
2549N–AVR–05/11
Pull-up and Bus-keeper
Timing
Figure 9-2.
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
these lines are tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
XMEM interface provides four different wait-states as shown in
tant to consider the timing specification of the External Memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the set-up requirement. The access time for the External Memory is defined to be the time from
receiving the chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data is stable
during a read sequence (see t
379
to divide the external memory space in two sectors with individual wait-state settings. This
makes it possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to
page 379
in the
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
- 382). The different wait-states are set up in software. As an additional feature, it is possible
“External Data Memory Timing” on page
38. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while
to
Table 31-18 on page 382
External SRAM Connected to the AVR
AVR
AD7:0
A15:8
ALE
WR
RD
LLRL
ATmega640/1280/1281/2560/2561
+ t
RLRH
and
- t
Figure 31-9 on page 382
DVRH
D
G
“XMCRB – External Memory Control Register B”
379.
in
Tables 31-11
Q
Table 9-3 on page
through
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
to
Figure 31-12 on page 384
Tables 31-18
Table 31-11 on
38. It is impor-
on pages
30
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