ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 159
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ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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2549N–AVR–05/11
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. For more information on the different
modes, see
Table 17-3.
Table 17-4
PWM mode.
Table 17-4.
Note:
COMnA1
COMnB1
COMnC1
COMnA1
COMnB1
COMnC1
0
0
1
1
0
0
1
1
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at BOTTOM.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
“Modes of Operation” on page
COMnA0
COMnB0
COMnC0
COMnA0
COMnB0
COMnC0
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
0
1
0
1
0
1
0
1
disconnected (normal port operation). For all other WGM1 settings, normal
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C
See “Fast PWM Mode” on page 150.
Clear OCnA/OCnB/OCnC on compare match, set OCnA/OCnB/OCnC at
Set OCnA/OCnB/OCnC on compare match, clear OCnA/OCnB/OCnC at
Clear OCnA/OCnB/OCnC on compare match (set output to low level)
Set OCnA/OCnB/OCnC on compare match (set output to high level)
ATmega640/1280/1281/2560/2561
Table 17-2 on page
Normal port operation, OCnA/OCnB/OCnC disconnected
Normal port operation, OCnA/OCnB/OCnC disconnected
port operation, OC1A/OC1B/OC1C disconnected
Toggle OCnA/OCnB/OCnC on compare match
148.
BOTTOM (non-inverting mode)
BOTTOM (inverting mode)
148. Modes of operation supported by the
Description
Description
for more details.
159
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