ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 466

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.7.2
Name:
Access Type:
Offset:
Reset Value:
This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register.
• INACK: Inhibit Non Acknowledge
• OVER: Oversampling Mode
• CLKO: Clock Output Select
• MODE9: 9-bit Character Length
• MSBF/CPOL: Bit Order or SPI Clock Polarity
32142A–12/2011
31
23
15
–
–
7
0: The NACK is generated.
1: The NACK is not generated.
0: Oversampling at 16 times the baud rate.
1: Oversampling at 8 times the baud rate.
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin unless USCLKS selects the external clock.
0: CHRL defines character length.
1: 9-bit character length.
If USART does not operate in SPI Mode:
MSBF=0: Least Significant Bit is sent/received first.
MSBF=1: Most Significant Bit is sent/received first.
If USART operates in SPI Mode, CPOL is used with CPHA to produce the required clock/data relationship between devices.
CPOL=0: The inactive state value of CLK is logic level zero.
CPOL=1: The inactive state value of CLK is logic level one.
Mode Register
CHMODE
CHRL
30
22
14
MR
Read-write
0x4
0x00000000
–
–
6
29
21
13
–
–
5
NBSTOP
USCLKS
INACK
28
20
12
–
4
OVER
27
19
11
–
3
ATUC64/128/256L3/4U
CLKO
PAR
26
18
10
2
MODE
MODE9
25
17
–
9
1
SYNC/CPHA
MSBF/CPOL
24
16
8
0
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