ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 566

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.8.2.2
23.8.2.3
32142A–12/2011
Setting Up and Performing a Transfer
Address Matching
TTOUT: Prescaled clock cycles used to time SMBUS timeout T
SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time T
EXP: Specifies the clock prescaler setting used for the SMBUS timeouts.
Figure 23-6. Bus Timing Diagram
Operation of the TWIS is mainly controlled by the Control Register (CR). The following list pres-
ents the main steps in a typical communication:
The interrupt system can be set up to generate interrupt request on specific events or error con-
ditions, for example when a byte has been received.
The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in
SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to
zero. NBYTES is updated by hardware, so in order to avoid hazards, software updates of
NBYTES can only be done through writes to the NBYTES register.
The TWIS can be set up to match several different addresses. More than one address match
may be enabled simultaneously, allowing the TWIS to be assigned to several addresses. The
address matching phase is initiated after a START or REPEATED START condition. When the
TWIS receives an address that generates an address match, an ACK is automatically returned
to the master.
3. Before any transfers can be performed, bus timings must be configured by writing to the
4. The Control Register (CR) must be configured with information such as the slave
Timing Register (TR).If the Peripheral DMA Controller is to be used for the transfers, it
must be set up.
address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and
which addresses to match.
S
t
t LOW
HD:STA
t
SU:DAT
t HIGH
t
HD:DAT
t LOW
t
t
SU:DAT
SU:STA
ATUC64/128/256L3/4U
Sr
TIMEOUT
.
t
SU:STO
SU_DAT
P
.
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