ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 96

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32142A–12/2011
• Detailed description
• Multi packet mode for IN endpoints
The data is written according to this sequence:
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. When the user clears FIFOCON, the next current bank may already be
clear and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on
details about the KILLBK bit.
Figure 8-10. Abort Algorithm
In multi packet mode, the user can prepare n USB packets in the bank to be sent on a multiple
IN transaction. The packet sizes will equal UECFGn.EPSIZE unless the AUTO_ZLP option is
• When the bank is empty, TXINI and FIFOCON are set, which triggers an EPnINT interrupt if
• The user acknowledges the interrupt by clearing TXINI.
• The user reads the UESTAX.CURRBK field to see which the current bank is.
• The user writes the data to the current bank, located in RAM as described by its descriptor:
• The user should write the size of the IN packet into the USB descriptor:
• The user allows the controller to send the bank contents and switches to the next bank (if
TXINE is one.
EPn_ADDR_BK0/1.
EPn_PCKSIZE_BK0/1.BYTE_COUNT.
any) by clearing FIFOCON.
Figure 8-10 on page
TXINEC = 1
EPRSTn = 1
Abort Done
NBUSYBK
Endpoint
Abort
== 0?
Yes
No
Yes
96. See
KILLBKS = 1
KILLBK
No
== 1?
”Endpoint n Control Register” on page 130
ATUC64/128/256L3/4U
Disable the TXINI interrupt.
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Wait for the end of the
procedure
Kill the last written bank.
for more
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