ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 81

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. USB Interface (USBC)
8.1
8.2
Table 8-1.
8.3
32142A–12/2011
pipe/endpoint
Features
Overview
Block Diagram
...
0
1
2
6
Description of USB pipes/endpoints
Mnemonic
Rev: 2.0.0.15
•
•
•
•
•
•
•
The Universal Serial Bus interface (USBC) module complies with the Universal Serial Bus (USB)
2.0 specification.
Each pipe/endpoint can be configured into one of several transfer types. It can be associated
with one or more memory banks (located inside the embedded system or CPU RAM) used to
store the current data payload. If two banks are used (“ping-pong” mode), then one bank is read
or written by the CPU (or any other HSB master) while the other is read or written by the USBC
core.
Table 8-1
PEP0
PEP1
PEP2
PEP6
The USBC interfaces a USB link with a data flow stored in the embedded ram (CPU or HSB).
The USBC requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock. For
more details see
speed or a 1.5MHz low-speed bit clock from the received USB differential data, and to transmit
data according to full- or low-speed USB device tolerances. Clock recovery is achieved by a dig-
ital phase-locked loop (a DPLL, not represented) in the USBC module, which complies with the
USB jitter specifications.
The USBC module consists of:
• HSB master interface
...
Compatible with the USB 2.0 specification
Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication
Seven physical pipes/endpoints in ping-pong mode
Flexible pipe/endpoint configuration and reallocation of data buffers in embedded RAM
Up to two memory banks per pipe/endpoint
Built-in DMA with multi-packet support through ping-pong mode
On-chip transceivers with built-in pull-ups and pull-downs
describes the hardware configuration of the USBC module.
1023 bytes
1023 bytes
1023 bytes
1023 bytes
”Clocks” on page
Max. size
...
available banks
84. The 48MHz clock is used to generate either a 12MHz full-
Number of
...
1
2
2
2
ATUC64/128/256L3/4U
Control/Isochronous/Bulk/Interrupt
Control/Isochronous/Bulk/Interrupt
Control/Isochronous/Bulk/Interrupt
Control/Isochronous/Bulk/Interrupt
Type
...
81