ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 692

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.6.8
28.6.9
28.6.10
28.6.11
32142A–12/2011
Mono
Alternative Upsampling Ratio
DMA operation
Interrupts
put of the DAC pins will have a voltage given by the following equation, given that it is configured
to run at the default upsampling ratio of 128:
If one want to get coherence between the sign of the input data and the output voltage one can
use the DATAN outputs or invert the sign of the input data by software.
When the Mono bit (MONO) in the Control Register is set, data written to SDR0 will be used for
both output channels. If one of the compact stereo formats are used only the data written to the
part of SDR0 that corresponds with channel 0 is used.
The digital filters and Sigma Delta modulators requires its own clock to perform the conversion at
the correct speed, and this clock is provided by a generic clock in the SCIF. The frequency of
this clock depends on the input sample rate and the upsampling ratio which is controlled by the
Alternative Upsampling Ratio bit (ALTUPR) in the Control Register.
The ABDACB supports three upsampling ratios, 125, 128, and 136. The default setting is a ratio
of 128, and is used when CR.ALTUPR is zero. Using this ratio gives a clock frequency require-
ment that is common for audio products. In some cases one may want to use other clock
frequencies that already are available in the system. By writing a one to CR.ALTUPR a upsam-
pling ratio of 125 or 136 is used depending on the configuration of the Sampling Frequency field
in the Control Register. Refer to
The required clock frequency of the generic clock can be calculated from the following equation:
R is the upsampling ratio of the converter. If CR.ALTUPR is zero the upsampling ratio is 128. If
CR.ALTUPR is one, R will change to 125 when CR.FS is configured for 8kHz, 12kHz, 16kHz,
24kHz, 32kHz, and 48kHz. For the other configurations of CR.FS, 11.025kHz, 22.050kHz, and
44.100kHz, it will change to 136.
The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA
Controller can be programmed to automatically transfer samples to the Sample Data Registers
(SDR0 and SDR1) when the Audio Bitstream DAC is ready for new samples. Two DMA chan-
nels are used, one for each sample data register. If the Mono Mode bit in the Control Register
(CR.MONO) is one, or one of the compact stereo formats is used, only the DMA channel con-
nected to SDR0 will be used. When using DMA only the Control Register needs to be written in
the Audio Bitstream DAC. This enables the Audio Bitstream DAC to operate without any CPU
intervention such as polling the Status Register (SR) or using interrupts. See the Peripheral
DMA Controller documentation for details on how to setup Peripheral DMA transfers.
The ABDACB requires new data samples at a rate of F
indicate when the system is ready to receive new samples. The Transmit Ready Interrupt Status
bit in the Status Register (SR.TXRDY) will be set whenever the ABDACB is ready to receive a
new sample. A new sample value must be written to the sample data registers (SDR0 and
V
OUT
Table 28-3
=
⎛
⎝
1
-- -
2
GCLK[Hz]
–
--------- -
128
33
SDR
----------- -
for required clock frequency and settings.
2
15
=
F
VOLUME
------------------------ -
S
2
15
ATUC64/128/256L3/4U
R 8
–
1
S
. The interrupt status bits are used to
⎞ V
⎠
VDDIO
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