ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 123
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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12. Interrupts and Programmable Multi-level Interrupt Controller
12.1
12.2
12.3
8077H–AVR–12/09
Features
Overview
Operation
•
•
•
•
Interrupts signal a change of state in peripherals, and this can be used to alter program execu-
tion. Peripherals can have one or more interrupts, and all are individually enabled. When the
interrupt is enabled and the interrupt condition is present this will generate a corresponding inter-
rupt request. All interrupts have a separate interrupt vector address.
The Programmable Multi-level Interrupt Controller (PMIC) controls the handling of interrupt
requests, and prioritizing between the different interrupt levels and interrupt priorities. When an
interrupt request is acknowledged by the PMIC, the program counter is set to point to the inter-
rupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts; low, medium
or high. Medium level interrupts will interrupt low level interrupt handlers. High level interrupts
will interrupt both medium and low level interrupt handlers. Within each level, the interrupt prior-
ity is decided from the interrupt vector address, where the lowest interrupt vector address has
the highest interrupt priority. Low level interrupts have an optional round-robin scheduling
scheme to ensure that all interrupts are serviced within a certain amount of time.
Non-Maskable Interrupts (NMI) are also supported.
Interrupts must be globally enabled for any interrupts to be generated. This is done by setting
the global interrupt enable bit (I-bit) in the CPU Status Register. The I-bit will not be cleared
when an interrupt is acknowledged. Each interrupt level must also be enabled before interrupts
with the corresponding level can be generated.
When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the
interrupt request. Based on the interrupt level and interrupt priority of any ongoing interrupts, the
interrupt is either acknowledged or kept pending until it has priority. When the interrupt request
is acknowledged, the program counter is updated to point to the interrupt vector. The interrupt
vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.
After returning from the interrupt handler, program execution continues from where it was before
the interrupt occurred. One instruction is always executed before any pending interrupt is
served.
The PMIC status register contains state information that ensures that the PMIC returns to the
correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an
interrupt handler. Returning from an interrupt will return the PMIC to the state it had before enter-
ing the interrupt. The Status Register (SREG) is not saved automatically upon an interrupt
Separate interrupt vector for each interrupt
Short, predictable interrupt response time
Programmable Multi-level Interrupt Controller
Interrupt vectors can be moved to the start of the Boot Section.
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
XMEGA A
123
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