ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 340

• Manufacturer Part Number: ATxmega16A4
• Manufacturer: Atmel Corporation

Specifications of ATxmega16A4

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.4.2
28.4.3
28.4.4
28.4.5
28.4.6
8077H–AVR–12/09
IDCODE; 0x3
SAMPLE/PRELOAD; 0x2
BYPASS; 0xf
CLAMP; 0x4
HIGHZ; 0x5
The active states are:
IDEOCE is mandatory and the instruction for selecting the 32 bit ID-Register as Data Register.
The ID-Register consists of a version number, a device number and the manufacturer code cho-
sen by JEDEC. This is the default instruction after power-up.
The active states are:
SAMPLE/RELOAD mandatory and the instruction for pre-loading the output latches and taking a
snapshot of the input/output pins without affecting system operation. However, the output
latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
Note that since each of the SAMPLE and PRELOAD instructions implements the functionality of
the other, they share a common binary value, and can be treated as one single merged
instruction.
The active states are:
BYPASS is mandatory and the instruction for selecting the Bypass Register for Data Register.
The active states are:
CLAMP is optional and the instruction for allowing the state of the input/output pins to be deter-
mined from the preloaded output latches. The Bypass register is selected as Data Register.
The active states are:
HIGHZ is optional and the instruction for putting all outputs in an inactive drive state (e.g. high
impedance). The Bypass register is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: Data in the Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
• Capture-DR: Data in the IDCODE Register is sampled into the Device Identification register.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
• Capture-DR: Loads a logic "0" into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
• Capture-DR: Loads a logical "0" into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
the output latches are not connected to the pins.
XMEGA A
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