ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 182

• Manufacturer Part Number: ATxmega16A4
• Manufacturer: Atmel Corporation

Specifications of ATxmega16A4

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.4
15.7
15.7.1
8077H–AVR–12/09
Register Description
On-Chip Debug
CTRL - Control Register
Lock Register. For more details refer to
Advanced Waveform Extension Lock Register” on page
When the lock bit is set, the Control Register A, the Output Override Enable Register and the
Fault Dedec.tion Event Mask register cannot be changed.
To avoid unintentional changes in the fault event setup it is possible to lock the Event System
channel configuration by writing the corresponding Event System Lock Register. For more
details refer to
Register” on page
When fault detection is enabled an OCD system receives a break request from the debugger,
this will by default function as a fault source. When an OCD break request is received, the
AWeX and corresponding Timer/Counter will enter fault state and the specified fault action(s) will
be performed.
After the OCD exits from the break condition, normal operation will be started again. In cycle-by-
cycle mode the waveform output will start on the first update condition after exit from break, and
in latched mode, the Fault Condition Flag must be cleared in software before the output will be
restored. This feature guarantees that the output waveform enters a safe state during break.
It is possible to disable this feature.
• Bit 7:6 - RES - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5 - PGM: Pattern Generation Mode
Setting this bit enables the pattern generation mode if set. This will override the DTI if enabled,
and the Pattern Generation reuses the dead-time registers for storing the pattern.
• Bit 4 - CWCM: Common Waveform Channel Mode
If this bit is set CC channel A waveform output will be used as input for all the dead-time genera-
tors. CC channel B, C, and D waveforms will be ignored.
• Bit 3:0 - DTICCxEN: Dead-Time Insertion CCx Enable
Setting these bits enables the Dead Time Generator for the corresponding CC channel. This will
override the Timer/Counter waveform outputs.
Bit
+0x00
Read/Write
Initial Value
R
7
0
-
”IO Memory Protection” on page 25
44.
6
R
0
-
PGM
R/W
5
0
”IO Memory Protection” on page 25
CWCM
R/W
4
0
DTICCDEN
R/W
3
0
and
45.
”EVSYSLOCK – Event System Lock
DTICCCEN
R/W
2
0
DTICCBEN
R/W
1
0
and
XMEGA A
DTICCAEN
R/W
”AWEXLOCK –
0
0
CTRL
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