ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 221
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.9.5
8077H–AVR–12/09
BAUD - TWI Baud Rate Register
• Bit 2 - BUSERR: Bus Error
The Bus Error (BUSERR) flag is set if an illegal bus condition has occurred. An illegal bus condi-
tion occurs if a Repeated START or STOP condition is detected, and the number of bits from the
previous START condition is not a multiple of nine. Writing a one to this bit location will clear the
BUSERR flag.
Writing the ADDR register will automatically clear the BUSERR flag.
• Bit 1:0 - BUSSTATE[1:0]: Bus State
The Bus State (BUSSTATE) bits indicate the current TWI bus state as defined in
The change of bus state is dependent on bus activity. Refer to the
Logic” on page
Table 19-5.
Writing 01 to the BUSSTATE bits forces the bus state logic into idle state. The bus state logic
cannot be forced into any other state. When the master is disabled, and after reset the Bus State
logic is disabled and the bus state is unknown.
The Baud Rate (BAUD) register defines the relation between the system clock and the TWI Bus
Clock (SCL) frequency. The frequency relation can be expressed by using the following
equation:
The BAUD register must be set to a value that results in a TWI bus clock frequency (f
or less 100 kHz or 400 kHz dependent on standard used by the application. The following equa-
tion [2] expresses equation [1] with respect to the BAUD value:
The BAUD register should be written while the master is disabled.
f
TWMBR
TWI
Bit
+0x04
Read/Write
Initial Value
=
BUSSTATE[1:0]
--------------------------------------- - [Hz]
2(5
=
+
------------- - 5
2f
00
01
10
11
f
TWMBR)
f
sys
TWI
sys
R/W
7
0
TWI master Bus State
212.
–
[2]
R/W
6
0
[1]
Group Configuration
UNKNOWN
R/W
5
0
OWNER
BUSY
IDLE
R/W
4
0
BAUD[7:0]
R/W
Description
Unknown Bus State
Idle
Owner
Busy
3
0
R/W
2
0
Section 19.4 ”TWI Bus State
R/W
1
0
XMEGA A
R/W
0
0
Table
TWI
) equal
BAUD
19-5.
221
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