ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 22
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ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16D4-AU
Manufacturer:
Atmel
Quantity:
438
Part Number:
ATxmega16D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega16D4-MH
Manufacturer:
Atmel
Quantity:
1 605
Company:
Part Number:
ATxmega16D4-MHR
Manufacturer:
SANYO
Quantity:
50
Part Number:
ATxmega16D4-MHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
4.8.1
4.9
4.10
4.11
4.12
4.12.1
8210B–AVR–04/10
Memory Timing
Device ID
IO Memory Protection
Register Description - NVM Controller
General Purpose I/O Registers
ADDR2 - Non-Volatile Memory Address Register 2
OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the
address range 0x00 - 0x1F, specific bit manipulating and checking instructions are available.
The I/O memory definition for an XMEGA device is shown in "Register Summary" in the device
datasheet.
The lowest 16 I/O Memory addresses is reserved for General Purpose I/O Registers. These reg-
isters can be used for storing information, and they are particularly useful for storing global
variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC
instructions.
Read and write access to the I/O Memory takes one CPU clock cycle. Write to SRAM takes one
cycle and read from SRAM takes two cycles. EEPROM page load (write) takes one cycle and
three cycles are required for read. For burst read, new data is available every second cycle.
External memory has multi-cycle read and write. The number of cycles depends on type of
memory.
Each device has a three-byte device ID which identifies the device. These registers identify
Atmel as the manufacturer of the device and the device type. A separate register contains the
revision number of the device.
Some features in the device is regarded to be critical for safety in some applications. Due to this,
it is possible to lock the IO register related to the Event System and the Advanced Waveform
Extensions. As long as the lock is enabled, all related IO registers are locked and they can not
be written from the application software. The lock registers themselves are protected by the
Configuration Change Protection mechanism, for details refer to
tion” on page
The ADDR2, ADDR1 and ADDR0 registers represents the 24-bit value ADDR.
• Bit 7:0 - ADDR[23:16]: NVM Address Register Byte 2
This register gives the data value byte 2 when accessing application and boot section.
Bit
+0x02
Read/Write
Initial Value
12.
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
ADDR[23:16]
R/W
3
0
R/W
2
0
”Configuration Change Protec-
R/W
1
0
XMEGA D
R/W
0
0
ADDR2
22