ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 273
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ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16D4-AU
Manufacturer:
Atmel
Quantity:
438
Part Number:
ATxmega16D4-AU
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
ATxmega16D4-MH
Manufacturer:
Atmel
Quantity:
1 605
Company:
Part Number:
ATxmega16D4-MHR
Manufacturer:
SANYO
Quantity:
50
Part Number:
ATxmega16D4-MHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
23.3
23.4
23.4.1
23.4.2
23.4.3
23.4.4
23.5
8210B–AVR–04/10
NVM Controller
NVM Commands
NVM Controller Busy
Action Triggered Commands
NVM Read Triggered commands
NVM Write Triggered Commands
CCP Write/Execute Protection
For both self-programming and external programming it is possible to run a CRC check on the
Flash or a section of the Flash to verify its content.
The device can be locked to prevent read and/or write of the NVM. There are separate lock bits
for external programming access, and self-programming access to the Boot Loader Section,
Application Section and Application Table Section.
All access to the Non Volatile Memories is done through the NVM Controller. This controls all
NVM timing and access privileges, and hold the status of the NVM. This is the common NVM
interface for both the external programming and self-programming. For more details on the NVM
Controller refer to
The NVM Controller has a set of commands that decide the task to perform on the NVM. This is
issued to the NVM Controller by writing the selected command to the NVM Command Register.
In addition data and addresses must be read/written from/to the NVM Data and Address regis-
ters for memory read/write operations.
When a selected command is loaded and address and data is setup for the operation, each
command has a trigger that will start the operation. Bases on the triggers, there are three main
types of commands.
Action triggered commands are triggered when the Command Execute (CMDEX) bit in the NVM
Control Register A (CTRLA) is written. Action triggered commands typically are used for opera-
tions which do not read or write the NVM such as the CRC check.
NVM read triggered commands are triggered when the NVM memory is read, and this is typically
used for NVM read operations.
NVM Write Triggered commands are triggered when the NVN is written, and this is typically
used for NVM write operations.
Most command triggers are protected from accidental modification/execution during self-pro-
gramming. This is done using the Configuration Change Protection (CCP) feature which
requires a special write or execute sequence in order to change a bit or execute an instruction.
For details on the CCP, refer to
When the NVM Controller is busy performing an operation, the Busy flag in the NVM Status
Register is set and the following registers are blocked for write access:
• NVM Command Register
• NVM Control A Register
• NVM Control B Register
• NVM Address registers
”Register Description” on page
”Configuration Change Protection” on page 12
294.
XMEGA D
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