ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 285
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ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16D4-AU
Manufacturer:
Atmel
Quantity:
438
Part Number:
ATxmega16D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega16D4-MH
Manufacturer:
Atmel
Quantity:
1 605
Company:
Part Number:
ATxmega16D4-MHR
Manufacturer:
SANYO
Quantity:
50
Part Number:
ATxmega16D4-MHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
23.10.5
8210B–AVR–04/10
NVM EEPROM Commands
For EEPROM page programming the ADDR register can be treated as having two section. The
least significant bits address the bytes within a page, while the most significant bits address the
page within the EEPROM. This is shown in
page (E2BYTE) is held by the bits [1:BYTEMSB] in the ADDR register. The remaining bits
[PAGEMSB:BYTEMSB+1] in the ADDR register holds the EEPROM page address (E2PAGE).
Together E2BYTE and E2PAGE holds an absolute address to a byte in the EEPROM. The size
of E2WORD and E2PAGE will depend on the page and flash size in the device, refer to the
device datasheet for details on this.
Figure 23-3. I/O mapped EEPROM addressing
When EEPROM memory mapping is enabled, loading a data byte into the EEPROM page buffer
can be performed through direct or indirect store instructions. Only the least significant bits of
the EEPROM address are used to determine locations within the page buffer, but the complete
memory mapped EEPROM address is always required to ensure correct address mapping.
Reading from the EEPROM can be done directly using direct or indirect load instructions. When
a memory mapped EEPROM page buffer load operation is performed, the CPU is halted for 3
cycles before the next instruction is executed.
When the EEPROM is memory mapped, the EEPROM page buffer load and EEPROM read
functionality from the NVM controller is disabled.
The NVM Flash commands that can be used for accessing the EEPROM through the NVM Con-
troller are listed in
For self-programming of the EEPROM the Trigger for Action Triggered Commands is to set the
CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Command is triggered
reading the NVM DATA0 register (DATA0).
E2PAGE
E2END
00
01
02
NVM ADDR
DATA MEMORY
BIT
Table
PAGE
WITHIN THE EEPROM
PAGEMSB
PAGE ADDRESS
23-4.
E2PAGE
Figure 23-3 on page
BYTEMSB
E2BYTE
BYTE ADDRESS
WITHIN A PAGE
0
285. The byte address in the
DATA BYTE
PAGE
XMEGA D
E2BYTE
00
01
02
E2PAGEEND
285