ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 38
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ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
953
21. USART
21.1
21.2
8067M–AVR–09/10
Features
Overview
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The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2 kbps.
PORTC, PORTD, PORTE, and PORTF each has two USARTs. Notation of these peripherals
are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1, USARTF0,
USARTF1, respectively.
Eight Identical USART peripherals
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High-resolution Arithmetic Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
Master SPI mode for SPI communication
IrDA support through the IRCOM module
XMEGA A1
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