ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 97
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
953
8067M–AVR–09/10
33. RTC Counter value not correctly read after sleep
34. Pending asynchronous RTC-interrupts will not wake up device
35. TWI, the minimum I
36. TWI address-mask feature is non-functional
37. TWI, a general address call will match independent of the R/W-bit value
38. TWI Transmit collision flag not cleared on repeated start
If EBI Power Reduction Bit is set while EBI is enabled, accessing external memory could
result in bus hang-up, blocking all further access to all data memory.
Problem fix/Workaround
Ensure that EBI is disabled before setting EBI Power Reduction bit.
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
If the TWI is in Master Read mode and issues a Repeated Start on the bus, this will immedi-
ately release the SCL line even if one complete SCL low period has not passed. This means
that the minimum SCL low time in the I2C specification could be violated.
Problem fix/Workaround
If this is a problem in the application, ensure in software that the Repeated Start is never
issued before one SCL low time has passed.
The address-mask feature is non-functional, so the TWI can not perform hardware address
match on more than one address.
Problem fix/Workaround
If the TWI must respond to multiple addresses, enable Promiscuous Mode for the TWI to
respond to all address and implement the address-mask function in software.
When the TWI is in Slave mode and a general address call is issued on the bus, the TWI
Slave will get an address match regardless of the received R/W bit.
Problem fix/Workaround
Use software to check the R/W-bit on general call address match.
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
2
C SCL low time could be violated in Master Read mode
XMEGA A1
97