ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 90
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ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
953
35. Errata
35.1
8067M–AVR–09/10
ATxmega128A1 rev. H
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Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
The ADC has up to ±2 LSB inaccuracy
ADC gain stage output range is limited to 2.4 V
Sampling speed limited to 500 ksps for supply voltage below 2.0V
ADC Event on compare match non-functional
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
The input difference between two succeeding ADC samples is limited by VREF
Increased noise when using internal 1.0V reference at low temperature
Configuration of PGM and CWCM not as described in XMEGA A Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
BODACT fuse location is not correct
Sampled BOD in Active mode will cause noise when bandgap is used as reference
DAC has up to ±10 LSB noise in Sampled Mode
DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
DAC refresh may be blocked in S/H mode
Conversion lost on DAC channel B in event triggered mode
Both DFLLs and both oscillators have to be enabled for one to work
Access error when multiple bus masters are accessing SDRAM
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
Low level interrupt triggered when pin input is disabled
JTAG enable does not override Analog Comparator B output
NMI Flag for Crystal Oscillator Failure automatically cleared
Flash Power Reduction Mode can not be enabled when entering sleep
Some NVM Commands are non-functional
Crystal start-up time required after power-save even if crystal is source for RTC
Setting PRHIRES bit makes PWM output unavailable
Accessing EBI address space with PREBI set will lock Bus Master
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI, the minimum I2C SCL low time could be violated in Master Read mode
TWI address-mask feature is non-functional
TWI, a general address call will match independent of the R/W-bit value
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag erroneously read as set
WDR instruction inside closed window will not issue reset
XMEGA A1
90