SAM3N1B Atmel Corporation, SAM3N1B Datasheet - Page 213

• Manufacturer Part Number: SAM3N1B
• Manufacturer: Atmel Corporation

Specifications of SAM3N1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 12-4. User Reset State
12.4.4.4
213
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
SAM3N
NRST
SLCK
NRST
MCK
Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These
commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:
The software reset is entered if at least one of these bits is set by the software. All these com-
mands can be performed independently or simultaneously. The software reset lasts 3 Slow
Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is
detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn-
chronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field
ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field
RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in
RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog-
ress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left.
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field
Resynch.
2 cycles
Any
Freq.
Any
system, and, in particular, the Remap Command. The Peripheral Reset is generally used for
debug purposes.
Except for debug purposes , PERRST must always be used in conjunction with PROCRST
(PERRST and PROCRST set both at 1 simultaneously).
ERSTL in the Mode Register (RSTC_MR).
>= EXTERNAL RESET LENGTH
Resynch.
2 cycles
XXX
Processor Startup
= 2 cycles
0x4 = User Reset
11011A–ATARM–04-Oct-10