SAM3N1B Atmel Corporation, SAM3N1B Datasheet - Page 491
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SAM3N1B
Manufacturer Part Number
SAM3N1B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1B
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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28.11 Two-wire Interface (TWI) User Interface
Table 28-6.
Note:
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Offset
0x00
0x04
0x08
0x0C
0x10
0x14 - 0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0xEC - 0xFC
0x100 - 0x124
1. All unlisted offset values are conisedered as “reserved”.
(1)
Register Mapping
Register
Control Register
Master Mode Register
Slave Mode Register
Internal Address Register
Clock Waveform Generator Register
Reserved
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Receive Holding Register
Transmit Holding Register
Reserved
Reserved for the PDC
TWI_CWGR
TWI_MMR
TWI_IADR
TWI_SMR
TWI_RHR
TWI_THR
TWI_IMR
TWI_IER
TWI_IDR
TWI_CR
TWI_SR
Name
–
–
–
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Access
–
–
–
0x0000F009
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
SAM3N
SAM3N
Reset
N / A
N / A
N / A
–
–
–
491
491
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