SAM3S2A Atmel Corporation, SAM3S2A Datasheet - Page 190
SAM3S2A
Manufacturer Part Number
SAM3S2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.21.15 System control block design hints and tips
190
SAM3S
Ensure software uses aligned accesses of the correct size to access the system control block
registers:
The processor does not support unaligned accesses to system control block registers.
In a fault handler. to determine the true faulting address:
Software must follow this sequence because another higher priority exception might change the
MMFAR or BFAR value. For example, if a higher priority handler preempts the current fault han-
dler, the other fault might change the MMFAR or BFAR value.
• except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses
• for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word accesses.
• Read and save the MMFAR or BFAR value.
• Read the MMARVALID bit in the MMFSR, or the BFARVALID bit in the BFSR. The MMFAR or
BFAR address is valid only if this bit is 1.
6500C–ATARM–8-Feb-11
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