SAM3S2A Atmel Corporation, SAM3S2A Datasheet - Page 871
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SAM3S2A
Manufacturer Part Number
SAM3S2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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36.6.5.2
36.6.5.3
6500C–ATARM–8-Feb-11
Changing the Duty-Cycle, the Period and the Dead-Times
Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the
value in the
Cycle Register”
Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than
1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value
from between 1 up to 14 in PWM_CDTYx Register. The resulting duty-cycle quantum cannot be
lower than 1/15 of the PWM period.
It is possible to modulate the output waveform duty-cycle, period and dead-times.
To prevent unexpected output waveform, the user must use the
Update Register”
Time Update Register”
waveform parameters while the channel is still enabled.
Note:
• If the channel is an asynchronous channel (SYNCx = 0 in
• If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and
• If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and
Register”
values until the end of the current PWM period and update the values for the next period.
UPDM = 0 in PWM_SCM register), these registers hold the new period, duty-cycle and dead-
times values until the bit UPDULOCK is written at “1” (in
Control Register”
values for the next period.
UPDM=1 or 2 in PWM_SCM register):
– registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-
– register PWM_CDTYUPDx holds the new duty-cycle value until the end of the
times values until the bit UPDULOCK is written at “1” (in PWM_SCUC register) and
the end of the current PWM period, then update the values for the next period.
update period of synchronous channels (when UPRCNT is equal to UPR in
Sync Channels Update Period Register”
PWM period, then updates the value for the next period
If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written
several times between two updates, only the last written value is taken into account.
“PWM Channel Period Register”
(PWM_SCM)), these registers hold the new period, duty-cycle and dead-times
(PWM_CDTYx) can help the user in choosing. The event number written in the
, the
(PWM_SCUC)) and the end of the current PWM period, then update the
“PWM Channel Period Update Register”
(PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx) to change
(PWM_CPRDx) and the
(PWM_SCUP)) and the end of the current
“PWM Sync Channels Update
“PWM Sync Channels Mode
and the
“PWM Channel Duty Cycle
“PWM Channel Dead
“PWM Channel Duty
SAM3S
“PWM
871
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