SAM3S2A Atmel Corporation, SAM3S2A Datasheet - Page 94
SAM3S2A
Manufacturer Part Number
SAM3S2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.12.4
10.12.4.1
10.12.4.2
10.12.4.3
10.12.4.4
10.12.4.5
94
STRBTEQ
LDRHT
SAM3S
LDR and STR, unprivileged
Syntax
Operation
Restrictions
Condition flags
Examples
R4, [R7]
R2, [R2, #8]
Load and Store with unprivileged access.
where:
op
type is one of:
cond
Rt
Rn
offset
These load and store instructions perform the same function as the memory access instructions
with immediate offset, see
these instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as nor-
mal memory access instructions with immediate offset.
In these instructions:
These instructions do not change the flags.
• Rn must not be PC
• Rt must not be SP and must not be PC.
op{type}T{cond} Rt, [Rn {, #offset}]
LDR
STR
B
SB
H
SH
-
; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
is one of:
Load Register.
Store Register.
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
“LDR and STR, immediate offset” on page
“Conditional execution” on page
; immediate offset
89. The difference is that
6500C–ATARM–8-Feb-11
84.
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