SAM3S2A Atmel Corporation, SAM3S2A Datasheet - Page 41
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SAM3S2A
Manufacturer Part Number
SAM3S2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.3.1
10.3.2
10.3.3
10.3.4
10.3.4.1
10.3.4.2
6500C–ATARM–8-Feb-11
System level interface
Integrated configurable debug
Cortex-M3 processor features and benefits summary
Cortex-M3 core peripherals
Nested Vectored Interrupt Controller
System control block
The Cortex-M3 processor provides multiple interfaces using AMBA
speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine grain memory
control, enabling applications to implement security privilege levels, separating code, data and
stack on a task-by-task basis. Such requirements are becoming critical in many embedded
applications.
The Cortex-M3 processor implements a complete hardware debug solution. This provides high
system visibility of the processor and memory through either a traditional JTAG port or a 2-pin
Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
These are:
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that sup-
ports low latency interrupt processing.
The System control block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• code-patch ability for ROM system updates
• power control optimization of system components
• integrated sleep modes for low power consumption
• fast code execution permits slower processor clock or increases sleep mode time
• hardware division and fast multiplier
• deterministic, high-performance interrupt handling for time-critical applications
• memory protection unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing.
®
technology to provide high
SAM3S
41
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