SAM3S2A Atmel Corporation, SAM3S2A Datasheet - Page 852
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SAM3S2A
Manufacturer Part Number
SAM3S2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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SAM3S
Figure 36-4. Non Overlapped Center Aligned Waveforms
Note:
When center aligned, the channel counter increases up to CPRD and decreases down to 0. This
ends the period.
When left aligned, the channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a
left aligned channel.
Waveforms are fixed at 0 when:
Waveforms are fixed at 1 (once the channel is enabled) when:
The waveform polarity must be set before enabling the channel. This immediately affects the
channel output level. Changes on channel polarity are not taken into account while the channel
is enabled.
Besides generating output signals OCx, the comparator generates interrupts in function of the
counter value. When the output waveform is left aligned, the interrupt occurs at the end of the
counter period. When the output waveform is center aligned, the bit CES of the PWM_CMRx
register defines when the channel counter interrupt occurs. If CES is set to 0, the interrupt
occurs at the end of the counter period. If CES is set to 1, the interrupt occurs at the end of the
counter period and at half of the counter period.
Figure 36-5 “Waveform Properties”
configuration.
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
• CDTY = CPRD and CPOL = 0
• CDTY = 0 and CPOL = 1
• CDTY = 0 and CPOL = 0
• CDTY = CPRD and CPOL = 1
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
OC0
OC1
1. See
Figure 36-5 on page 853
No overlap
Period
for a detailed description of center aligned waveforms.
illustrates the counter interrupts in function of the
6500C–ATARM–8-Feb-11
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