SAM3S2A Atmel Corporation, SAM3S2A Datasheet - Page 55
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SAM3S2A
Manufacturer Part Number
SAM3S2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.5.1.1
10.5.1.2
10.5.1.3
10.5.1.4
10.5.1.5
10.5.2
6500C–ATARM–8-Feb-11
Memory system ordering of memory accesses
Normal
Device
Strongly-ordered
Shareable
Execute Never (XN)
The processor can re-order transactions for efficiency, or perform speculative reads.
The processor preserves transaction order relative to other transactions to Device or Strongly-
ordered memory.
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
The additional memory attributes include.
For a shareable memory region, the memory system provides data synchronization between
bus masters in a system with multiple bus masters, for example, a processor with a DMA
controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, software must ensure data
coherency between the bus masters.
Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an
XN region causes a memory management fault exception.
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing this does not affect the behavior of the instruction sequence. Nor-
mally, if correct program execution depends on two memory accesses completing in program
order, software must insert a memory barrier instruction between the memory access instruc-
tions, see
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before
A2 in program order, the ordering of the memory accesses caused by two instructions is:
Where:
- Means that the memory system does not guarantee the ordering of the accesses.
Device access, non-shareable
A1
Device access, shareable
Strongly-ordered access
“Software ordering of memory accesses” on page
Normal access
A2
Normal
access
-
-
-
-
Non-shareable
Device access
<
<
-
-
Shareable
<
<
-
-
57.
Strongly-
ordered
access
<
<
<
-
SAM3S
55
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